Talk:Motorola 6800

category

So what's with the removal of the category? I don't know of any policy against categorizing microprocessors, so removing a category should be just as bad as deleting correct content. Stan 16:27, 15 Jul 2004 (UTC)

inserted

Inserted a link to the instruction set summary, since it's so hard to find on the net using google. Dave.

6800

I've added all that I know about the 6800 (having at least programmed them when I was younger). I could not find more information about the designers- if you know more, please add the information. Joe. —Preceding unsigned comment added by Jhallenworld (talk • contribs) 15:00, 4 November 2007 (UTC)

6800 CLOCK signal

I suggest we should include the signal requirement for "CLOCK" signal, its interesting that it needs 2 non overlapping signal. —The preceding unsigned comment was added by 222.124.209.153 (talk) 20:19, 4 April 2007 (UTC).

M6800 Patents

• Patent number: 3962682

Split low order internal address bus for microprocessor.

Inventor: Thomas H. Bennett

• Patent number: 3968478

Chip topography for MOS interface circuit.

Inventors: William D. Mensch, Jr

• Patent number: 3975712

Asynchronous communication interface adaptor

Inventors: Edward C. Hepworth, Rodney J. Means, Charles I. Peddle

• Patent number: 3979730

Interface adaptor having control register.

Inventors: Thomas H. Bennett, Earl F. Carlow, Edward C. Hepworth, William D. Mensch, Jr., Charles I. Peddle, Gene A. Schriber, Michael F. Wiles

• Patent number: 3979732

Asynchronous status interlock circuit for interface adaptor

Inventors: Edward C. Hepworth, Rodney J. Means

• Patent number: 3987418

Chip topography for MOS integrated circuitry microprocessor chip

Inventor: John K. Buchanan

• Patent number: 4003028

Interrupt circuitry for microprocessor chip.

Inventors: Thomas H. Bennett, Earl F. Carlow, Anthony E. Kouvoussis, Rodney H. Orgill, Michael F. Wiles

• Patent number: 4004281

Microprocessor chip register bus structure.

Inventors: Thomas H. Bennett, Anthony E. Kouvoussis, Michael F. Wiles

• Patent number: 4004283

Multiple interrupt microprocessor system.

Inventors: Thomas H. Bennett, Earl F. Carlow, Charles Peddle, Michael F. Wiles

• Patent number: 4006457

Logic circuitry for selection of dedicated registers

Inventors: Edward C. Hepworth, Rodney J. Means, Charles I. Peddle

• Patent number: 4010448

Interrupt circuitry for microprocessor chip

Inventors: Thomas H. Bennett, Earl F. Carlow, Anthony E. Kouvoussis, Rodney H. Orgill, Michael F. Wiles

• Patent number: 4016546

Bus switch coupling for series-coupled address bus sections in a microprocessor

Inventors: Thomas H. Bennett, Earl F. Carlow, Anthony E. Kouvoussis, Rodney H. Orgill, Charles Peddle, Michael F. Wiles

• Patent number: 4020472

Master slave registers for interface adaptor.

Inventors: Thomas H. Bennett, Earl F. Carlow, Edward C. Hepworth, Wilbur L. Mathys, William D. Mensch, Jr., Rodney H. Orgill, Charles I. Peddle, Michael F. Wiles

• Patent number: 4030079

Processor including incrementor and program register structure.

Inventors: Thomas H. Bennett, Earl F. Carlow, Anthony E. Kouvoussis, Rodney H. Orgill, Charles Peddle, Michael F. Wiles

• Patent number: 4032896

Microprocessor having index register coupled to serial-coupled address bus

Inventors: Thomas H. Bennett, Earl F. Carlow, Anthony E. Kouvoussis, Rodney H. Orgill, Charles Peddle, Michael F. Wiles

• Patent number: 4037204

Microprocessor interrupt logic.

Inventors: Thomas H. Bennett, Earl F. Carlow, Anthony E. Kouvoussis, Rodney H. Orgill, Charles Peddle, Michael F. Wiles

• Patent number: 4040035

Microprocessor having index register coupled to serial-coupled address bus

Inventors: Thomas H. Bennett, Earl F. Carlow, Anthony E. Kouvoussis, Rodney H. Orgill, Charles Peddle, Michael F. Wiles

• Patent number: 4069510

Interrupt status register for interface adaptor chip.

Inventors: Earl F. Carlow, Michael F. Wiles

• Patent number: 4071887

Synchronous serial data adaptor

Inventors: Thomas C. Daly, Edward C. Hepworth, Rodney J. Means

• Patent number: 4086627

Interrupt system for microprocessor system.

Inventors: Thomas H. Bennett, Earl F. Carlow, Edward C. Hepworth, Wilbur L. Mathys, William D. Mensch, Jr., Rodney H. Orgill, Charles I. Peddle, Michael F. Wiles

• Patent number: 4087855

Valid memory address enable system for a microprocessor system.

Inventors: Thomas H. Bennett, Earl F. Carlow, Edward C. Hepworth, Wilbur L. Mathys, William D. Mensch, Jr., Rodney H. Orgill, Charles I. Peddle, Michael F. Wiles

• Patent number: 4090236

N-channel field effect transistor integrated circuit microprocessor.

Inventors: Thomas H. Bennett, Earl F. Carlow, Anthony E. Kouvoussis, Rodney H. Orgill, Charles Peddle, Michael F. Wiles

• Patent number: 4145751

Data direction register for interface adaptor chip.

Inventors: Earl F. Carlow, Wilbur L. Mathys, William D. Mensch, Charles Peddle, Michael F. Wiles

• Patent number: 4218740

Interface adaptor architecture.

Inventors: Thomas H. Bennett, Earl F. Carlow, Edward C. Hepworth, William D. Mensch, Jr., Charles I. Peddle, Gene A. Schriber, Michael F. Wiles

• Patent number: 4263650

Digital data processing system with interface adaptor having programmable.

Inventors: Thomas H. Bennett, Earl F. Carlow, Edward C. Hepworth, Wilbur L. Mathys, William D. Mensch, Jr., Rodney H. Orgill, Charles I. Peddle, Michael F. Wiles

--SWTPC6800 (talk) 06:55, 22 December 2009 (UTC)

References

• "Motorola joins microprocessor race with 8-bit entry". Electronics. 47 (47). McGraw-Hill: pp. 29–30. March 7, 1974. {{cite journal}}: |pages= has extra text (help)

• Young, Link (April 19, 1974). "N-channel MOS technology yields new generation of microprocessors". Electronics. 47 (8). McGraw-Hill: pp. 88–95. {{cite journal}}: |pages= has extra text (help); Unknown parameter |coauthors= ignored (|author= suggested) (help) Authors with Motorola Semiconductor Products, Phoenix, Az. Describes M6800 family.

-- SWTPC6800 (talk) 03:49, 24 April 2010 (UTC)

The name

Anybody knows why it's called 6800? I know it follows common number series of that era (think of Intel 8000/8080 or 82xx series, "TTL" 74xx, etc.). I'm just wondering if 68xx was the next product line after "67xx" or how they came up with that number. Or was it just the marketing department at Motorola that wanted the product(s) to look 'technological' & 'hi-tech' so they opted for a labelling and marketed it in accordance with that era's "way of doing it"?

174.6.87.98 (talk) 03:23, 15 May 2010 (UTC)

I believe the name was derived from the year the project was started, which I believe was 1968. But I could be mistaken. - Johnlogic (talk) 21:42, 29 April 2016 (UTC)

The Pricing

The big thing lacking from most of these microprocessor articles is the pricing. Initial pricing at the time of release is the absolute must. Usually these prices varied according to the quantity ordered. Also, if the info is available, it would be good to see how the price changed through the years. Maybe a section on Marketing is called for to contain this information. JettaMann (talk) 14:27, 10 September 2010 (UTC)

Wiki

Hi all, I was advised to come here by User:swtpc6800 to not "use an ambiguous template". So, the article needs to get some wikilinks inside it. It's (very?) well-referenced, but there was not even a link to Motorola, the manufacturer. I'm not familiar with microprocessor articles, so I don't know if the sections/text is up to scratch, but for general readers... I'd say it needs a bit of work, for example there's no explanation of common computer terminology (RAM, ROM, ICs [I had to look it up, I guess this is the correct meaning??], I/o, etc) and the article seems a little complicated at first glance.

When I have some time I will be coming back to improve the article where I can, although I think a template would definitely be helpful for any editors, as it's easiest indication of a 'to-do' list on an article :) - ChrisWar666 (talk) 19:45, 13 July 2011 (UTC)

Usually the "Wiify" tag is applied to blocks of text that have no formatting or internal links at all; it's not as useful in flagging an article that already has some internal structure and links. If you find you have to look up a term to understand it, then that's a good term to have as an internal link. --Wtshymanski (talk) 20:43, 13 July 2011 (UTC)

Irrelevant content

It seems to me that the majority of this article has little if anything to do with the 6800 series - a lot of it is the history of Motorola or of microprocessors generally. I'm reluctant to simply delete this stuff but it certainly doesn't belong here. Opinions? ﬥ (talk) 19:57, 24 February 2012 (UTC)

Context is a good thing and it's hard to find exciting photos of microprocessors, but there are a couple of images here that look only barely relevant (shirt pocket radio and a silicon wafer). Andy Dingley (talk) 20:08, 24 February 2012 (UTC)

Context is very important. How many readers know that Motorola was one of the largest semiconductor companies in the world and not just a fading cell phone supplier? The history of the development of the MC6800 is under reported and often wrong. Chuck Peddle is frequently listed as "one of the key designers of the Motorola 6800". A major problem with the MC6800 was yield, how do you give an overview of the problem without covering the production process? I was the principle author of this version but I don't claim ownership. Could you point to some good content in other microprocessor articles here on Wikipedia? -- SWTPC6800 (talk) 01:59, 25 February 2012 (UTC)

Those aspects should be covered, but they don't need to be illustrated to such an extent.

In particular, any images of silicon wafers should be of comparable processes to the designs under discussion: similar size wafers, similar size dice and a similar technology for the geometry. Wafers can look radically different across the decades. If the point is that a wafer could only make a few dice, and that only a few of these dice passed their tests, that's communicated far better by a wafer that shows such a small number of dice, not a modern wafer that's three times the diameter and has maybe a hundred times as many dice upon it. Andy Dingley (talk) 10:45, 25 February 2012 (UTC)

If Motorola had met their design goal of 180 mils, the 3 inch wafer would hold over 200 die. While I provided pictures of authentic MC6800 ICs, I don't own any 3 inch wafers. The wafer photo I selected from the Commons clearly shows how the wafer contains many individual chips. It holds around 500 die while a better example would hold 200 to 300 die. I think it is close enough to illustrate the concept. -- SWTPC6800 (talk) 18:25, 25 February 2012 (UTC)

Context is valuable up to a point. Enough about Motorola and the general state of microprocessors at the time to aid understanding of the 6800-the subject of the article-are all well and good article. This article goes far beyond that; much of it reads like a comparitive analysis of the 6800 and the 8080. A description of one microprocessor's architecture shouldn't include comparrisons to another one in every second or third sentence. There is even a brief passage about the 8080's design heritage! I'm not any sort of 6800 expert, but I'm about ready to edit out the superfluous material all the same. -- Joe Avins (talk) 02:36, 30 January 2013 (UTC)

I agree. I came to this talk page specifically to contribute my observation that in this article there is much too much about the Intel 8080, appearing too frequently, considering that the article's subject is the Motorola 6800. Now, I very much like the 8080 and its descendants (including the 8085, the Z80, and the too-maligned 8086 and 8088), and I am much more familiar with it—including actual practical experience (with the 8085)—than with the 6800, but when I came to this article, I was seeking to learn specifically about the 6800 and its technical evolution. Having that interest, which I think is fairly typical for a reader of this article, I found the extensive and repeated comparison to the 8080—including not just technical features and details but competitive history, such as the dates when design layout started for both CPUs (rather than just for the 6800)—distracting and tangential. A few mentions of competitive history, e.g. the dates that other competing 8-bit CPUs such as the 8080 became available in large-scale production, and their prices, are relevant, but I believe the extensive comparison here belongs in a different article, perhaps one dedicated to the general history of the 8-bit microprocessor and microcontroller market during the 1970s. (Slightly aside, having read about halfway through this article, I did not yet know if the 6800 had any other significant competitor besides the 8080, in the time frame of 1974–1975. By the middle of this article, I think the reader ought to know, being by that point so well aware of the 8080 as one competitor.) In conclusion, I do not think this is a bad article, and I do appreciate the work of the original author, which exhibits considerable knowledge, understanding, and language (writing) skill, but the excess off-topic (out-of-scope) information is a definite flaw that needs improvement. 173.49.122.138 (talk) 03:29, 3 July 2019 (UTC)

I agree, this article has vastly exceeded its scope. It's not to say that it's not interesting or useful information, but it belongs on other pages, because much of it is general information that isn't specific to the 6800. -- tooki (talk) 01:10, 18 August 2014 (UTC)

intel 8080, z80 and Motorola 6800

intel 8080, z80 and Motorola 6800 have only one Index register and 1 accumulator. While intel 8008 have 8 16-bit index registers and 7 14-bits address registers (including program pointer) for nesting (call and return operations, or simply JUMPs). So 6800 and 8080 can be called and returned only one time and intel 8008 can be called and to return many times, because have many address registers and each address register is saved (only 7 nestings). When finishing some miniprogram CPU can return to previsous program [address] 7 times. For 8080 it's said that it can do nessting infinityly (hard to believe it's using RAM for saving address of rom lockation for instruction). So either 8080 can return only one time or somehow it have more advanced interapt functioning from I/O devices ( maybe they having another CPU and feeding during interapt, till say some wire on signal, instructions address... and then interapt ends it returns to previous program). Or maybe 8086 and 8088 is much more smart and fallowing patern of working design of 4004 and 8008 and not of stolen 8080 from say Z80. Because 4004 have also 4 12-bits address nesting stack (4 levels of nesting) like 8008 and, if not lieing [and I remember correctly], like 8086. — Preceding unsigned comment added by Paraboloid01 (talk • contribs) 19:43, 10 September 2012 (UTC)

On page 6 (or 200) Motorola 6800 datasheet is expalined that there nessting is RAM:

"Stack Pointer (SP)

The stack pointer is a two byte register that contains the address of the next available location in an external push-down/pop-up stack. This stack is normally a random access Read/Write memory that may have any location (address) that is convenient. In those applications that require storage of information in the stack when power is lost, the stack must be non-volatile."

In over words stack can be PROM (programable ROM), so lost of power don't brake program... But in general, 8080 and 6800 and Z80 for nesting of return addresses using RAM or there some mind f**k and no need more than one return (or thats why 8080, Z80 and 6800 don't become IBM personal computers). — Preceding unsigned comment added by Paraboloid01 (talk • contribs) 20:20, 10 September 2012 (UTC)

Here idea how CPU can work and get input/output from many devices, without interrupt from I/O devices. First, there is ROM which holds microcode for running some primitive program. This program then [depending on input/output] loads from keyboard or HDD more complex program to RAM. Something like this. The hardest thing is to how made loop to 1000000000 and at same time during this execution of loop check and execute keyboard, mouse and over I/O signals. So first loop of say "for a:=1 to 1234567899 do" (Free Pascal version which supports up to 2^31=2147483648) need to divide by 1000. Then we get 1234567899/1000=1234567.899. So there is 1234567 loops from 1 to 1000 and additional 1 loop from 1 to 899. for last loop (from 1 to 899) execution need each time check if "a" is not more than 899 and if "a" is more then 899, then terminate the program, which running this loop (and return result and so on). So before this loop "for a:=1 to 1234567899 do" we need to get input from mouse keyboard and over I/O devices. We first check all inputs with specific opcode (like do it 4004 (intel 4004 can get about 16 inputs/outputs)), then we starting doing loop "from 1 to 1000" just one time and result saving in memory. There is actually say such code:

c:=0;
c:=c+1/sqrt(a);  //first time
c:=c+1/sqrt(a); //second time
c:=c+1/sqrt(a); //third time
................ // n-th time
c:=c+1/sqrt(a); //1000th time

and for such code need about 1000 bytes or little bit more (maybe 8000 or 4000 bytes). This code is first loaded into RAM as I/O check code before this code. So when we finishing 1000th line, we have leaved here [after last 1000th line] instruction to save computed result "c" and subtract 1 from 1234567 (we get 1234566). Then we have fallowing instruction to jump to first address to serve interrupts. Then everything repeating. CPU checking position of mouse (because not need such frequently to check and mouse position signal must hold about few microseconds or less like mouse wheel signals and keyboard signals) and keybord signals and executing only 1 mouse right-click, 1 left-click and over inputs only one time and so for keyboard. After this we AGAIN doing loop from "1 to 1000" [executing 1000 lines] and subtracting 1 from 1234566 and saving result 1234565 to memory RAM.

Answering Parabaloid01's comments, some CPUs have the stack as a register file internal to the CPU, and the CPU has a small internal counter to track which location in the stack is the most recent return address. The 8080, Z80, (6502), and 6800 instead have a stack pointer which points into RAM, and the stack pointer keeps track of which return address saved in RAM is the most recent. See, for example, section 3.1, "Stack and Stack Pointer" and section 3.2, "Saving MPU Status" in Motorola's Programming Reference Manual for the 6800 for a description of the use of the 6800's stack.

The mention of ROM and PROM here seems to indicate a misunderstanding of Read-Only Memory. Memory that can't be written to cannot be used to save return addresses or any other MPU state. The section of the Hitachi manual being referred to is, rather, indicating that some hardware applications might require having the stack pointer point into battery backed-up RAM. Reiisi (talk) 02:28, 21 September 2020 (UTC)

References

6801 instruction count

The article states that the 6801 had 10 new instructions but it looks like the datasheet lists 16. I could not find the "Product Preview MC6801" attributed in the references to confirm.97.40.64.122 (talk) 04:38, 29 October 2017 (UTC)

We can find the additions listed in Table 4-1, "MC6801 Additional Instructions" on page 4-10 of Motorola's 6801 reference manual: ABX, ADDD, ASLD/LSLD, BHS, BLO, BRN, JSR, LDD, LSL, LSRD, MUL, PSHX, PULX, STD, SUBD, CPX.

Of these, ASLD/LSLD are just two mnemonics for the same instruction. BHS, BLO, and LSL are new mnemonics (new names) for existing instructions. JSR has an additional addressing mode, so it is not exactly a new instruction, but there is a new op-code for the new addressing mode. And CPX is not a new instruction, but has new semantics (new function and the required support circuitry).

So there are fifteen new instructions recognized by the Motorola assembly language software (6801 Assembler); one instruction has additional (new) valid syntax, and one instruction is safe to use in a broader context.

Counting actual completely new instructions, we would set aside BHS, BLO, LSL, and one or the other of ASLD/LSLD. JSR and CPX could be counted either way, depending on what one means by "new", thus, either eleven or thirteen new instructions.

Counting new op-codes would require referring to other lists and/or the detailed instruction descriptions, or to the op-code chart. In my head, I look at the list and count ABX (1), ADDD (4), ASLD/LSLD (1), BHS (0), BLO (0), BRN (1), JSR (1), LDD (4), LSL (0), LSRD (1), MUL (1), PSHX (1), PULX (1), STD (3), SUBD (4), CPX (0), which adds up to twenty-three new op-codes. Reiisi (talk) 03:09, 21 September 2020 (UTC)

Note that checking with a data sheet or other manual material for the 6802 will show that it includes none of these new instructions or changed semantics. Reiisi (talk) 03:13, 21 September 2020 (UTC)

References

Relatively unknown in the microcomputer field, why?

This article mentions a few uses in the microcomputer field, but fails to mention the obvious - the 6800 was pretty much unused compared to the competition from Intel, Zilog and MOS. Cost was certainly one factor in this, at least until the 1976 time frame when that fell to be similar to the 6502, but that doesn't explain it all (especially considering the 8080 was a similar price yet required a more complex 3-voltage supply).

The part that's missing is performance. On every contemporary benchmark - and there's not that many of them so it's difficult to find - the 6800 invariably finishes behind every other CPU. The Rugg/Feldman_benchmarks are a BASIC test, and one can see the difference a change of the interpreter makes, but comparing Altair BASIC 1.1 times (MS 8k w/strings) on the Altair 680 and 8800 one can see a significant difference in performance.

By the time the Byte Sieve rolled around the 6800 had already been abandoned, but even the 6809 puts in a terrible show, being outperformed by the PET of 4 years earlier.

I think this needs to be mentioned, so if anyone has additional sources from the era that would be very useful.

Maury Markowitz (talk) 12:59, 18 November 2019 (UTC)

BASIC benchmarks have very little to do with the performance of the CPU and more to do with the care that the engineers put into writing the interpreters. I'll try to comment further, when I have time.Reiisi (talk) 03:19, 21 September 2020 (UTC)

PDP-8 or PDP-11?

"65816/65802 Assembly-Language Programming", author Michael Fischer says, "The 6800 was designed on a shoestring budget. The 6800 came out in February 1974 and was based on the architecture of the then relatively popular PDP-8 minicomputer. It was designed as a compromise between a controller and a general-purpose processor, which resulted in an instruction set that was not especially useful for either application

Sounds like a reputable source. Do we have conflicting stories on this? Maury Markowitz (talk) 13:03, 18 November 2019 (UTC)

It's an absurd statement, which you'll see if you take the trouble to read about the PDP-8 and the PDP-11, and look at the instruction sets. But this is Wikipedia - no fact-checking done here. TEDickey (talk) 20:45, 18 November 2019 (UTC)

So absurd that I wrote to Terry Ritter, initiator of the 6809 project, who stated that neither statement is correct and the designs were influenced by the best concepts the could afford to implement.

I tracked down the original reference that makes this claim. It is a single parenthetical passage in a section that is not about the 6800, and it is the only mention of the 6800 in the entire book.

I suggest removing the claim until we find independent support. Maury Markowitz (talk) 12:41, 19 November 2019 (UTC)

Something like that. 6809 was a later revision (we're talking about the 6800). 6800 of course had fewer registers, and only 8-bit data, but in operations (and addressing) was generally observed to have been influenced by the PDP-11 (for example this). For PDP-8, that would be unlikely (do take the time to read about it). But removing the entire statement seems appropriate. TEDickey (talk) 21:09, 19 November 2019 (UTC)

I believe that the text in "A History of Modern Computing" that TEDickey referenced must be a typo. Few would argue that the 68000 (three zeros) was PDP-11 influenced. But it is difficult to find any similarities between the 6800 (two zeros) and PDP-11. They don't share addressing modes, registers, or orthogonality. Just look at the 6800 block move example. The main loop for this simple operation is a clunky 14 instructions for something that can be coded in two PDP-11 or 68000 instructions. The referenced book is copyrighted 1998, so the 68000 was certainly known, and even obsolete by then. Clearly a typo. On page 289 of that same book it says the 68000's "design was very much in the spirit of PDP-11 and VAX." Check out the WD16 to see a processor surely inspired by the PDP-11. RastaKins (talk) 16:27, 21 September 2023 (UTC)

not a typo. The resemblance between 6800 and PDP-11 was the set of operations rather than the addressing modes. Rather than using up the encoding with registers, the 6800 provided a good set of operations and the ability to combine those with the stack. The 68K came around while the PDP-11 was becoming obsolete by the VAX. This may help. You may find this helpful as well. TEDickey (talk) 22:21, 21 September 2023 (UTC)

You clearly have deep knowledge of the PDP-11 in order to write a PDP-11 disassembler and a 6800 assembler/simulator so I am surprised you think there is some PDP-11 inspiration in the architecture of the 6800. You mention the good number of 6800 operations that can be combined with the stack. I see NO 6800 arithmetic or logical operations that reference the stack. (PDP-11 can perform any operation on stack.) X can't even be PUSHed and PULLed by itself. (PDP-11 can PUSH or PULL anything and even push immediate.) A, B and X are not fungible. Few operations can be performed between A and B, only ADD and compare. You can add B to A but not A to B. I admit there are a few PDP-11 features that exist in the 6800 that don't exist on the 8080: TST, BIT, and NEG, signed integers, and relative branches. That's a very short list. RastaKins (talk) 02:59, 22 September 2023 (UTC)

You've mistaken my comment: the push/pop operations are separate instructions, but those instructions are readily combined with the arithmetic/logical instructions to save intermediate results and use them later. In some other (contemporary of course) microprocessors with more registers, the designs tend to do that data movement as special cases. The PDP-11's instruction set has few special cases, and of course has addressing modes embedded in the (16-bit) instructions which wouldn't fit in the (8-bit) 6800 instructions. (The immediate-data or address-offset in subsequent 16-bit or 8-bit chunks doesn't count here) TEDickey (talk) 00:30, 23 September 2023 (UTC)

Just my opinion, but a quick refresh of my memory: PDP-8 has one accumulator, now dedicated index registers; PDP-11 has a small bank of general purpose registers which can be used as both accumulators and index registers. The 680X series has two accumulators and one to four index registers. Well, the 6805 has only one accumulator, but it has an index register. We see more influence from the addressing modes of the PDP-11 than from the selection of a register set. Comparative with other CPU architectures, the 680X and 680X0 are closer to the PDP-11 than some other well-known CPUs, but the best we could say and be honest is that the designs of most modern CPUs were instructed by, not based on or derived from, the architecture of the PDP series. And they were instructed by several other CPUs, as well. Reiisi (talk) 03:31, 21 September 2020 (UTC)

Relationship of 6801 and 6802

The current page includes a paragraph that says the 6801 contains a 6802 core, which is a mistake that can be verified by examination of relevant manuals and data sheets. As mentioned in the talk section about instruction counts, the 6801 includes new instructions. See the 6801 reference manual and compare with, for example, the 6802 data sheet available in various places on the web.Reiisi (talk) 03:42, 21 September 2020 (UTC)

References